1. Field of the Invention
The present invention relates to a voltage-controlled oscillating circuit, and more particularly, to a voltage-controlled oscillating circuit capable of altering an oscillating frequency according to a control voltage and to a phase-locked loop circuit, a so-called PLL circuit, equipped with the voltage-controlled oscillating circuit.
2. Description of the Background Art
In order to cooperatively operate a plurality of internal circuits implemented on the same system, employed are phase-locked loop circuits (PLL circuit) each generating a synchronized clock. Especially, in recent years, an LSI (Large Scale Integrated Circuit) has experienced progress toward its higher speed operation in company with miniaturization; as a result, a margin in phase shift between a clock of the entire system on which an LSI is implemented and an internal clock of the LSI has become narrowed, which in turn, has enhanced a chance of usage of a PLL circuit to compensate a phase shift.
As a result, many of PLL circuits are required to be incorporated, which leads to increase in design load in order to output synchronized clocks corresponding to a wide frequency range. Accordingly, it is important to make an output frequency range (lock range) of a PLL circuit as wide as possible and thereby, cover a necessary frequency range with a single PLL circuit.
Since a lock range of a PLL circuit is largely dependent on an output frequency range of a voltage-controlled oscillator included, it is important to ensure a wide output frequency range of the voltage-controlled oscillating circuit. A general configuration of such a voltage-controlled oscillating circuit is shown, for example in FIG. 2 of Japanese Patent Laying-Open No. 9-200001(1997). The general configuration of a voltage-controlled oscillating circuit disclosed in the publication is hereinafter referred to the prior art.
FIG. 12 is a circuit diagram representing a configuration of the prior art voltage-controlled oscillating circuit 70.
Referring to FIG. 12, the voltage-controlled oscillating circuit 70 has a ring oscillator constructed from inverters at three stages. The ring oscillator includes: an inverter formed of a P-channel transistor 51a and an N-channel transistor 51b; an inverter formed of a P-channel transistor 52a and an N-channel transistor 52b; and an inverter formed of a P-channel transistor 53a and an N-channel transistor 53b. Capacitors 51c, 52c and 53c to determine a delay value of the ring oscillator are coupled with output nodes of the respective inverters.
The voltage-controlled oscillating circuit 70 includes: a P-channel transistor 54 receiving a fixed voltage Vf at the gate thereof; a P-channel transistor 55 receiving a control voltage Vc at the gate thereof; and N-channel transistors 56 and 57 constituting a current mirror circuit.
The voltage-controlled oscillating circuit 70 further includes: P-channel transistors 59, 60 and 61 each, coupled between a corresponding one of the inverters at three stages and a power source node supplying a power source voltage Vdd, and for controlling operating currents supplied to the respective inverters; and a transistor 58 constituting a current mirror circuit together with the transistor 59.
The voltage-controlled oscillating circuit 70 still further includes: N-channel transistors 62, 63 and 64 each, coupled between a corresponding one of ground nodes supplying a ground voltage Vss and a corresponding one of the inverters.
In the voltage-controlled oscillating circuit 70, the ring oscillator constituted of the inverters at three stages performs an oscillating operation. An oscillating frequency of the ring oscillator is determined in the following way.
Into the transistor 56, there flows the sum of a current flowing between the drain and source of the transistor 54 receiving the fixed voltage Vf at the gate thereof and a current flowing between the drain and source of the transistor 55 receiving the control voltage Vc at the gate thereof. The current flowing between the drain and source of the transistor 55 is controlled by the controlled voltage Vc.
Since the transistors 56 and 57 constitute a current mirror circuit, currents equal to each other flow through the respective transistors 56 and 57 and the current of the transistor 57 flows through the transistor 58. Since the transistors 58 and 59 constitute a current mirror circuit, duplicated current flows through the transistor 59. Furthermore, into the P-channel transistors 60 and 61 for current controlling, there flow currents proportional to respective size ratios of the transistors 60 and 61 to the transistor 59 (or the transistor 58). Likewise, into the N-channel transistors 62, 63 and 64 for current controlling, there flow currents proportional to respective size ratios of the transistors 62, 63 and 64 to the transistor 57 (or the transistor 56).
In such a configuration, an oscillating frequency is determined by operating currents flowing through the respective inverters at three stages constituting the ring oscillator and values of the delay capacitors 51c, 52c and 53c. The capacitors 51c, 52c and 53c determine delay times at the respective stages as load capacitances of the respective inverters constituting the ring oscillator.
Hence, an oscillating frequency of the voltage-controlled oscillating circuit 70 is altered by changing the control voltage Vc inputted to the gate of the transistor 55 to change each of operating currents flowing through the respective inverters constituting the ring oscillator. Furthermore, since operating currents flowing through the respective inverters of the ring oscillator are also altered by changing a set value of the fixed voltage Vf inputted to the transistor 54; therefore, an oscillating frequency differs under the same control voltage Vc applied. In other words, obtained are a plurality of oscillating frequency vs. control voltage Vc characteristics with a fixed voltage Vf as a parameter.
However, the prior art voltage-controlled oscillating circuit 70 determines operating currents for the respective inverters constituting the ring oscillator through voltage to current conversion according to the inputted control voltage Vc. As a result, a clock CLKO having an oscillating frequency corresponding to operating currents of the inverters is outputted from the ring oscillator.
Therefore, since a configuration is adopted of controlling an oscillating operation of the ring oscillator by a current value, it is difficult to broaden an oscillating frequency range. For this reason, it is also difficult to realize a PLL with a wide lock range even if a PLL circuit is constructed using such as voltage-controlled oscillating circuit.
Moreover, as a typical cause for jitter (phase deviation) occurring in a clock generated by the PLL circuit, there can be named noise on a power source voltage pulse (hereinafter simply referred to as power source noise).
At this point, referring again to FIG. 12, when noise occurs in the power source voltage Vdd supplied by the power source node, source voltages of the current control P-channel transistors 58, 59, 60 and 61 are directly varied; therefore, an influence of the power source noise is directly exerted on operating currents for the inverters constituting the ring oscillator, with the result that an oscillating frequency of the voltage-controlled oscillating circuit 70 is also affected directly by the power source noise.
Therefore, a regulator circuit or a filter circuit for reducing power source noise was required for use of the prior art voltage control oscillating circuit 70.
FIG. 13 is a circuit diagram representing a configuration of a filter circuit provided correspondingly to a power source voltage of the voltage-controlled oscillating circuit 70.
Referring to FIG. 13, a filter circuit 71 includes: a smoothing capacitance 72 coupled between the power source node 75 and the ground node supplying the ground voltage Vss; and a resistance element 73 coupled in series with the power source node 75. The filter circuit 71 prevents a high frequency component superimposed on the power source Vdd, that is noise, from being transmitted to the power source node 75 using a low pass filter formed by the smoothing capacitance 72 and the resistance element 73.
However, in the case where such a filter circuit 71 is employed, a voltage level of the power source node 75 drops when a value of the resistance element 73 is large. Hence, in order that a cut-off frequency determined by a product of a resistance value of the resistance element 71 and a capacitance value of the smoothing capacitance 72 is made sufficiently low, a capacitance value of the smoothing capacitance 72 has to be larger. As a result, an occupancy area of the smoothing capacitance 72 increases, which produces a problem that layout design becomes limited.
It is an object of the present invention to provide configurations of a voltage-controlled oscillating circuit having a wide output frequency range and capable of suppressing an influence of power source noise and of a phase-locked loop circuit equipped with the voltage-controlled oscillating circuit.
The present invention will be summarized as follows: According to a first aspect of the present invention, the present invention is directed to a voltage-controlled oscillating circuit receiving supply of a power source voltage to operate and comprises: a voltage generating circuit; and a ring oscillator circuit. The voltage generating circuit sets a voltage level of a bias voltage according to a control voltage inputted from outside. The voltage generating circuit includes: an operational amplifier, which is an amplifier of a single-stage configuration, and receiving supply of the power source voltage to operate. The operational amplifier has: first and second input terminals electrically coupled with one of the control voltage and a reference voltage and the other of the voltages, respectively; and an output terminal outputting the bias voltage. The voltage generating circuit further includes: a feedback circuit coupled between the output terminal and one of the first and second input terminals. The ring oscillator circuit generates a clock having a frequency corresponding to the bias voltage. The ring oscillator circuit has an odd-number of inverters, interconnected in a closed ring, and each inverter receiving supply of the bias voltage to operate.
Hence, a main advantage of the present invention is in that an oscillating frequency of the ring oscillator is controlled by the bias voltage generated by the voltage generating circuit including a single-stage operational amplifier excellent in frequency characteristics; therefore, there can be realized a voltage-controlled oscillating circuit excellent in frequency characteristics and capable of generating a clock with a small variation in phase in a stable way.
According to a second aspect of the present invention, the present invention is directed to a voltage-controlled oscillating circuit receiving a power source voltage to operate and comprises: a voltage generating circuit; and a ring oscillator circuit. The voltage generating circuit receives a control voltage and amplifies the control voltage at a prescribed amplification factor to generate a bias voltage of a voltage level different from that of the control voltage. The ring oscillator circuit generates a clock having a frequency according to that of the bias voltage. The ring oscillator circuit has an odd number of inverters interconnected in a closed ring and receives supply of the bias voltage at each of the converters to operate.
Hence, in the voltage-controlled oscillating circuit according to the present invention, an oscillating frequency of the ring oscillator is controlled by the bias voltage generated by the voltage shifting circuit including the operational amplifier. Therefore, an adverse influence due to power source noise can be suppressed to perform stable generation of a clock having a small variation in phase.
According to a third aspect of the present invention, the present invention is directed to a phase-locked loop circuit generating an output clock for operating an internal circuit in synchronism with a reference clock and comprises: a phase comparator circuit; a control circuit; and a voltage-controlled oscillating circuit. The phase comparator circuit compares the reference clock with a feedback clock from the internal clock. The control circuit sets a voltage level of a control voltage based on a phase comparison result of the phase comparator circuit. The voltage-controlled oscillating circuit receives supply of a power source voltage to operate and supply the output clock having a frequency according to the control voltage to the internal circuit. The voltage-controlled oscillating circuit includes: a voltage generating circuit setting a voltage level of a bias voltage according to the control voltage. The voltage generating circuit has: an operational amplifier, which is an amplifier of a single-stage configuration, and receiving supply of the power source voltage to operate. The operational amplifier has: first and second input terminals electrically coupled with one of the control voltage and a reference voltage and the other of the voltages, respectively; and an output terminal outputting the bias voltage. The voltage generating circuit further includes: a feedback portion coupled between the output terminal and one of the first and second terminals. The voltage-controlled oscillating circuit further includes: a ring oscillator circuit generating a clock, as the output clock, having a frequency according to that of the bias voltage. The ring oscillator circuit has: an odd-number of inverters, interconnected in a closed ring, and each inverter receiving supply of the bias voltage to operate.
Furthermore, a phase-locked loop circuit according to the present invention controls an oscillating frequency of an output clock of the voltage-controlled oscillating circuit with the bias voltage generated by the voltage generating circuit including the operational amplifier excellent in frequency characteristics. Therefore, an adverse influence can be suppressed that would otherwise be exerted on the output clock by power source noise without affecting stability of the entire phase-locked loop circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.